The present invention relates to color demodulation apparatuses and, more specifically, to an apparatus color-modulating a chrominance subcarrier signal separated from a composite television video signal through digital processing.
With recent advances in video quality, digitalization of television video signals has been required. To cope with digitalization, a color demodulation apparatus such as disclosed in Japanese Patent Laid-Open Publication No. 8-140114 (hereinafter referred to as prior document) has been suggested for color signal demodulation.
The conventional color demodulation apparatus disclosed in the above prior document is described below.
FIG. 11 shows a block diagram illustrating the configuration of the conventional color demodulation apparatus disclosed in the above prior document.
In FIG. 11, the conventional color demodulation apparatus includes a BPF circuit 101, multiplier circuits 102 to 104, first LPF circuits 105 and 106, accumulator circuits 107 and 108, second LPF circuits 109 and 110, a VCO circuit 111, a SIN data generator circuit 112, and a comparator circuit 113.
The BPF circuit 101 is a band-pass filter circuit allowing passage of the frequency band of a chrominance subcarrier signal. The BPF circuit 101 is supplied with the chrominance subcarrier signal separated from a composite digital video signal, and eliminates signal components of an unnecessary frequency band. According to gain control from the comparator circuit 113 which will be described later, the multiplier circuit 102 controls its output to keep a predetermined amplitude with respect to the received chrominance subcarrier signal. This control is generally called Auto Color Control (hereinafter referred to as ACC). The multiplier circuit 103 is supplied with the chrominance subcarrier signal after ACC processing outputted from the multiplier circuit 102, and multiplies the chrominance subcarrier signal by a 90-degree-phase-shifted SIN wave signal outputted from the SIN data generator circuit 112 for R-Y demodulation. The multiplier circuit 104 is supplied with the chrominance subcarrier signal after ACC processing outputted from the multiplier circuit 102, and multiplies the chrominance subcarrier signal by a 180-degree-phase-shifted SIN wave signal outputted from the SIN data generator circuit 112 for B-Y demodulation. The first LPF circuit 105 is a low-pass filter allowing passage of the frequency band of an R-Y signal, eliminating predetermined high frequency band components (such as noise) from a signal after demodulation by the multiplier circuit 103 and then outputting the R-Y signal. The first LPF circuit 106 is a low-pass filter allowing passage of the frequency band of a B-Y signal, eliminating predetermined high frequency band components (such as noise) of a signal after demodulation by the multiplier circuit 104 and then outputting the B-Y signal.
The R-Y signal from the first LPF circuit 105 is fed to the accumulator circuit 107. The accumulator circuit 107 accumulates the R-Y signal during a burst signal period of one horizontal period, that is, a burst signal according to a burst gate pulse (hereinafter referred to as BGP) from a horizontal deflection apparatus (not shown). The accumulated the burst signal is supplied through the second LPF circuit 109 to the VCO circuit 111. The VCO circuit 111 is a voltage controlled oscillator circuit capable of varying the period of a ramp wave, which is an output signal therefrom, according to the magnitude of a received signal. According to the received accumulated burst signal, the VCO circuit 111 controls the period of the ramp wave to be outputted to synchronize with that of the burst signal. Using the ramp wave from the VCO circuit 111, the SIN data generator circuit 112 generates a 90-degree-phase-shifted SIN signal and a 180-degree-phase-shifted SIN signal with respect to the period of the ramp wave, and then outputs the 90-degree-phase-shifted SIN signal to the multiplier circuit 103 and the 180-degree-phase-shifted SIN signal to the multiplier circuit 104.
By constituting a feedback loop as described above (hereinafter referred to as first feedback loop), the conventional color demodulation apparatus can perform accurate R-Y and B-Y demodulation always in synchronization with the burst signal.
On the other hand, the B-Y signal from the first LPF circuit 106 is fed to the accumulator circuit 108. Like the above, the accumulator circuit 108 accumulates a burst signal according to a BGP from the horizontal deflection apparatus. The accumulated the burst signal is supplied through the second LPF circuit 110 to the comparator circuit 113. The comparator circuit 113 has a predetermined reference value therein, and compares the value of the accumulated burst signal from the second LPF circuit 110 with the reference value. The comparator circuit 113 then controls gain of the multiplier circuit 102 so that the value of the accumulated burst signal matches the reference value.
By constituting a feedback loop as described above (hereinafter referred to as second feedback loop), the conventional color demodulation apparatus can always obtain a constant color signal amplitude.
In the conventional color modulation apparatus, however, the circuit for R-Y demodulation (the multiplier circuit 103 and the first LPF circuit 105) and the circuit for B-Y demodulation (the multiplier circuit 104 and the first LPF circuit 106) are formed individually. Furthermore, part of the circuits constituting the first feedback loop (the accumulator circuit 107 and the second LPF circuit 109) and part of the circuits constituting the second feedback loop (the accumulator circuit 108 and the second LPF circuit 110) are provided individually.
Therefore, the above conventional color demodulation apparatus has plural multiplier circuits, accumulator circuits, and LPF circuits, all or part thereof performing similar operation, thereby making the apparatus large in size.
Therefore, an object of the present invention is to provide a color demodulation apparatus having color demodulation capabilities as the conventional ones, with its size reduced by sharing part of processing circuits therein.
The present invention has the following features to solve the problem above.
A first aspect of the present invention is directed to a color demodulation apparatus color-demodulating a chrominance subcarrier signal separated from a composite television video signal through digital processing, comprising:
a frequency divider circuit for generating a predetermined load clock (hereinafter referred to as RCLK) using a system clock (hereinafter referred to as SCLK) which is an operational reference for the apparatus;
a band-pass filter circuit, supplied with the chrominance subcarrier signal, for eliminating signal components of an unnecessary frequency band from the chrominance subcarrier signal;
a first multiplier circuit, supplied with the chrominance subcarrier signal from the band-pass filter circuit, for controlling the chrominance subcarrier signal to be outputted therefrom to keep constant amplitude according to gain controlled by a comparator circuit;
a second multiplier circuit, supplied with the chrominance subcarrier signal after amplitude control outputted from the first multiplier circuit and a phase alternate SIN wave signal outputted from a SIN data generator circuit, for multiplying the signals together for multiplex demodulation of an R-Y signal and a B-Y signal;
a first low-pass filter circuit, supplied with a multiplex-demodulated signal from the second multiplier circuit, for passing frequency bands of the R-Y signal and the B-Y signal and eliminating predetermined high frequency band components;
a first load hold circuit, supplied with the multiplex-demodulated signal with the high frequency band components eliminated outputted from the first low-pass filter circuit, for separating the multiplex-demodulated signal into the R-Y signal and the B-Y signal and outputting the R-Y and B-Y signals according to the RCLK;
an accumulator circuit, supplied with the multiplex-demodulated signal with the high frequency band components eliminated outputted from the first low-pass filter circuit, for accumulating burst signal in the R-Y signal and burst signal in the B-Y signal based on a burst gate pulse (hereinafter referred to as BGP) which provides a burst signal period and outputting each of the accumulated burst signal only once during each horizontal period;
a second low-pass filter circuit, supplied with each burst signal outputted from the accumulator circuit, for passing the frequency bands of the R-Y signal and the B-Y signals and eliminating predetermined high frequency band components;
a second load hold circuit, supplied with each of the burst signal with the high frequency components eliminated outputted from the second low-pass filter circuit, for separating the burst signal into burst signal in the R-Y signal and burst signal in the B-Y signal and outputting each of the burst signal according to the RCLK;
a VCO circuit, supplied with the burst signal in the R-Y signal outputted from the second load hold circuit, for varying and outputting a period of a ramp wave according to a level of the burst signal in the R-Y signal;
a switching circuit, supplied with data corresponding to an R-Y demodulation axis and data corresponding to a B-Y demodulation axis in the ramp wave outputted from the VCO circuit, for alternately switching between the data for output according to the RCLK;
an adder circuit for adding data outputted from the switching circuit to data on the ramp wave outputted from the VCO circuit and outputting a ramp wave;
the SIN data generator circuit for generating and outputting the phase alternate SIN wave signal in synchronization with the ramp wave outputted from the adder circuit; and
the comparator circuit, supplied with the burst signal in the B-Y signal outputted from the second load hold circuit, for comparing a value of the burst signal with a predetermined reference value and controlling the gain of the first multiplier circuit so that the value of the burst signal matches the reference value.
As described above, in the first aspect, the color demodulation apparatus is realized by using a multiplex demodulation technique, with circuitry configuration sharing the portion for R-Y demodulation and the portion for B-Y demodulation, and part of the portions constituting the first feedback loop for keeping the amplitude of the chrominance subcarrier signal outputted from the first multiplier circuit constant and part of the portions constituting the second feedback loop for accurate R-Y and B-Y demodulation always in synchronization with the burst signals in the second multiplier circuit. Thus, since plural circuits each performing similar processing are not required, the color demodulation apparatus can be reduced in size.
A second aspect of the present invention is directed to a color demodulation apparatus color-demodulating a chrominance subcarrier signal separated from a composite television video signal through digital processing, comprising:
a frequency divider circuit for generating a predetermined RCLK using a SCLK which is an operational reference for the apparatus;
a band-pass filter circuit, supplied with the chrominance subcarrier signal, for eliminating signal components of an unnecessary frequency band from the chrominance subcarrier signal;
a first multiplier circuit, supplied with the chrominance subcarrier signal from the band-pass filter circuit, for controlling the chrominance subcarrier signal to be outputted therefrom to keep constant amplitude according to gain controlled by a comparator circuit;
a second multiplier circuit, supplied with the chrominance subcarrier signal after amplitude control outputted from the first multiplier circuit and a phase alternate SIN wave signal outputted from a SIN data generator circuit, for multiplying the signals together for multiplex demodulation of an R-Y signal and a B-Y signal;
a first low-pass filter circuit, supplied with a multiplex-demodulated signal from the second multiplier circuit, for passing frequency bands of the R-Y signal and the B-Y signal and eliminating predetermined high frequency band components;
a first load hold circuit, supplied with the multiplex-demodulated signal with the high frequency band components eliminated outputted from the first low-pass filter circuit, for separating the multiplex-demodulated signal into the R-Y signal and the B-Y signal and outputting the R-Y and B-Y signals according to the RCLK;
an accumulator circuit, supplied with the multiplex-demodulated signal with the high frequency band components eliminated outputted from the first low-pass filter circuit, for accumulating burst signal in the R-Y signal and burst signal in the B-Y signal based on a BGP which provides a burst signal period and outputting each of the accumulated burst signal only once during each horizontal period;
a second load hold circuit, supplied with each of the burst signal with the high frequency band components eliminated outputted from the accumulator circuit, for separating the burst signal into the burst signal in the R-Y signal and the burst signal in the B-Y signal and outputting each of the burst signal;
a second low-pass filter circuit, supplied with the burst signal in the R-Y signal outputted from the second load hold circuit, for passing the frequency band of the R-Y signal and eliminating predetermined high frequency band components;
a third low-pass filter circuit, supplied with the burst signal in the B-Y signal outputted from the second load hold circuit, for passing the frequency band of the B-Y signal and eliminating predetermined high frequency band components;
a VCO circuit, supplied with the burst signal in the R-Y signal with the high frequency band components eliminated outputted from the second low-pass filter circuit, for varying and outputting a period of a ramp wave according to a level of the burst signal;
a switching circuit, supplied with data corresponding to an R-Y demodulation axis and data corresponding to a B-Y demodulation axis in the ramp wave outputted from the VCO circuit, for alternately switching between the data for output according to the RCLK;
an adder circuit for adding data outputted from the switching circuit to data on the ramp wave outputted from the VCO circuit and outputting a resultant ramp wave;
the SIN data generator circuit for generating and outputting the phase alternate SIN wave signal in synchronization with the ramp wave outputted from the adder circuit; and
the comparator circuit, supplied with the burst signal in the B-Y signal with the high frequency band components eliminated outputted from the third low-pass filter circuit, for comparing a value of the burst signal and a predetermined reference value and controlling the gain in the first multiplier circuit so that the value of the burst signal matches the reference value.
As described above, in the second aspect, the color demodulation apparatus is realized by using a multiplex demodulation technique, with circuitry configuration sharing the portion for R-Y demodulation and the portion for B-Y demodulation, and part of the portions constituting a first feedback loop for keeping the amplitude of the chrominance subcarrier signal outputted from the first multiplier circuit constant and part of the portions constituting a second feedback loop for accurate R-Y and B-Y demodulation always in synchronization with the burst signals in the second multiplier circuit. Thus, since plural circuits each performing similar processing are not required, the color demodulation apparatus can be reduced in size.
Furthermore, in the second aspect, the second low-pass filter circuit for band-limiting the burst signal to be outputted to the VCO circuit and the third low-pass filter circuit for band-limiting the burst signal to be outputted to the comparator circuit are separately provided. Thus, it is possible to make a difference between the frequency characteristics in the first feedback loop and in the second feedback loop, thereby realizing color demodulation of higher image quality.
According to third and fourth aspects, in the first and second aspects, respectively,
the accumulator circuit comprises:
an adder circuit for adding an input signal and a signal outputted from an AND circuit together and outputting a resultant signal;
(2xc3x97n) latch circuits each delaying the signal outputted from the adder circuit according to timing of the SCLK;
a gain adjuster circuit for adjusting a delay signal outputted as an output signal from a last of the latch circuits with predetermined gain; and
the AND circuit, supplied with the BGP, for outputting a signal outputted from the gain adjuster circuit to the adder circuit only during a period of the BGP.
According to fifth to eighth aspects, in the first to fourth aspects, respectively,
each of the first to third low-pass filter circuits comprises:
(2xc3x97n) latch circuits each delaying an input signal according to timing of the SCLK;
a first gain adjuster circuit for adjusting a delay signal outputted from a last of the latch circuits with predetermined gain;
a second gain adjuster circuit for adjusting an input signal with predetermined gain; and
an adder circuit for adding a signal outputted from the first gain adjuster circuit and a signal outputted from the second gain adjuster circuit together and outputting a resultant signal as an output signal.
According to ninth and tenth aspects, in the first and second aspects, respectively,
each of the first to third low-pass filters and the accumulator circuit comprises:
a first adder circuit for adding an input signal and a signal outputted from an AND circuit together and outputting a resultant signal;
(2xc3x97n) first latch circuits each delaying the signal outputted from the first adder circuit according to timing of the SCLK;
a first gain adjuster circuit for adjusting a delay signal outputted as an output signal from a last of the first latch circuits with predetermined gain;
the AND circuit, supplied with the BGP, for outputting a signal outputted from the first gain adjuster circuit to the first adder circuit only during a period of the BGP;
(2xc3x97n) second latch circuits each delaying the delay signal outputted from the last of the first latch circuits as output signals according to timing of the SCLK;
a second gain adjuster circuit for adjusting a delay signal outputted from a last of the second latch circuits with predetermined gain;
a third gain adjuster circuit for adjusting the delay signal outputted as an output signal from the last of the first latch circuits with predetermined gain; and
a second adder circuit for adding a signal outputted from the second gain adjuster circuit and a signal outputted from the third gain adjuster circuit together and outputting a resultant signal as an output signal.
As described above, the third to tenth aspects indicate detailed structures of the first to third low-pass filter circuits and the accumulation circuit in the first and second aspects. Thus, according to the third to tenth aspects, by using even-numbered latch circuits for delay, the color modulation apparatus can perform filtering to pass R-Y and B-Y signals after multiplexing and can also accumulate these signals, without damaging them (that is, it is possible to perform filtering and accumulation of R-Y and B-Y signals separately).